Structure and method to preserve STI during etching

ABSTRACT

Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to the manufacture of semiconductordevices, particularly to a method and of protecting a single trenchisolation oxide from etching during epitaxial precleaning and thesemiconductor structure formed thereby.

[0003] 2. Discussion of the Related Art

[0004] The etching of shallow trench isolation (STI) oxides duringselective epitaxial precleaning for raised source-drain applicationspresents a problem in thin silicon-on-insulator (SOI) and othertechnologies. Cleaning the Si surface prior to epitaxial growth iscritical to the quality of the growth of the epitaxial layer. This isimportant because the device performance is strongly dependent on theeptiaxial film quality. Typically, the cleaning process involves theremoval of surface contamination and also involves Si surfacepassivation by hydrogen termination to prevent contamination fromadsorbing onto the surface prior to epitaxial growth. Pre-silicidecleaning also has strict requirements. In order to create high qualitysilicide without defects, it is necessary to clean and also to hydrogenpassivate the Si surface. Standard cleaning and hydrogen passivationchemistries include hydrofluoric acid (HF), which, in addition tocleaning Si, causes the unwanted etching of STI. In order to clean theSi surface adequately for epitaxial growth or silicide formation, theSTI is excessively etched. This is particularly problematic for thin SiSOI applications. The reason for this is that the STI thickness isdirectly proportional to the Si thickness and will therefore be thin forthin Si SOI. During the pre-epitaxial growth cleaning and or thepre-silicide cleaning, the entire STI may be etched. After the STI isgone, the Buried Oxide (BOX) layer begins to etch. The BOX is locateddirectly under the active area and as the BOX etches away, it canundercut the active area. When the undercutting is excessive, the activearea may peel away completely, thereby ruining the device.

[0005] Conventional STI is created by first forming a pad oxide layer onthe Si substrate, then SiN is deposited and patterned by lithography andetching. The SiN is used as a hard mask to etch trenches in the Si, thena thin SiO2 liner is formed by thermal oxidation. Finally, the STI oxideis deposited and chemical mechanical polishing (CMP) used to removesilicon oxide from areas outside the shallow trench. To avoid thepossibility of excessive STI etching during pre-epitaxial orpre-silicide cleaning, one solution is to deposit a protective nitrideliner inside the trench after the formation of the oxide liner butbefore the STI fill deposition. There are two main disadvantages to thismethod. The first problem is that the upper part of the nitride linerwill get etched during removal of the pad nitride layer, resulting in adivot adjacent to the active region. The divot is subsequently filledwith polysilicon during gate polysilicon deposition and the polysiliconin the divot can cause unwanted electrical connections between adjacentgates and also create a so-called “wraparound” gate. The wraparound gateresults in a lowering of the threshold voltage, which causes prematureactivation of the transistors. The second problem is that a nitridelayer cannot protect any STI oxide on top of it. All of the STI oxideabove it can be etched away, thereby compromising planarity. What isneeded is a method of protecting the shallow trench isolation (STI)during oxide etching processes.

SUMMARY OF THE INVENTION

[0006] Disclosed is a method of protecting a semiconductor shallowtrench isolation (STI) oxide from etching, the method comprisinglowering, if necessary, the upper surface of said STI oxide to a levelbelow that of adjacent silicon active areas, depositing a nitride linerupon said STI oxide and adjacent silicon active areas in a mannereffective in defining a depression above said STI oxide, filling saiddepression with a protective film, removing said nitride layer from saidadjacent active areas.

[0007] In another aspect of the invention said deposition of a nitrideliner is effected with a chemical vapor deposition.

[0008] In another aspect of the invention said chemical vapor depositionis one selected from a low pressure chemical vapor deposition, a rapidthermal chemical vapor deposition, a plasma-enhanced chemical vapordeposition, or a high-density plasma chemical vapor deposition.

[0009] In another aspect of the invention said chemical vapor depositionfurther comprises reacting a silane derivative with ammonia.

[0010] In another aspect of the invention said protective film is anorganic polymer.

[0011] In another aspect of the invention said organic polymer is aplanarizing polymer.

[0012] In another aspect of the invention said planarizing protectivepolymer is an anti-reflective coating polymer.

[0013] In another aspect of the invention said anti-reflective coatingpolymer is one selected from mixtures of acrylates and methacrylates,mixtures of polyurea and polysulfone polymers, and copolymers ofbenzophenone and bisphenol-A.

[0014] In another aspect of the invention said planarizing protectivepolymer is a photo-resist polymer.

[0015] In another aspect of the invention, said photo-resist polymer isa novolak resin.

[0016] In another aspect of the invention said protective film is aspin-on oxide.

[0017] In another aspect of the invention said protective film isconformal and is planarized by chemical mechanical polishing.

[0018] In another aspect of the invention said filling of saiddepression with protective film comprises depositing a layer of saidprotective film over said nitride layer, recessing said protective filmsuch that said protective film remains only in said depression.

[0019] In another aspect of the invention said protective film is anorganic polymer and said recessing is effected with a plasma etch.

[0020] In another aspect of the invention said protective film isremoved from said depression.

[0021] In another aspect of the invention, said protective film isremoved from said depression with a reactive ion etch.

[0022] Disclosed is a method of protecting a semiconductor shallowtrench isolation (STI) oxide from etching, the method comprisinglowering, if necessary, the upper surface of said STI oxide to a levelbelow that of adjacent silicon active areas, executing a chemical vapordeposition to deposit a conformal nitride liner upon said STI oxide andadjacent silicon active areas in a manner effective in defining adepression above said STI oxide, covering said nitride liner with aprotective film comprising an organic polymer, recessing said protectivefilm with a plasma etch, such that said protective film remains only insaid depression, removing said nitride layer from said adjacent activeareas with a reactive ion etch, removing said protective film from saiddepression with a plasma etch.

[0023] Disclosed is a semiconductor structure, comprising a plurality ofactive areas separated by one or more shallow trench isolations whereinonly said shallow trench isolations are covered by a protective layer ofsilicon nitride.

[0024] Disclosed is a semiconductor structure comprising a plurality ofactive areas separated by one or more shallow trench isolations, saidactive areas and shallow trench isolations covered by a layer of siliconnitride, wherein said layer of silicon nitride comprises depressionsover said shallow trench isolations, a protective film disposed in saiddepressions.

[0025] Disclosed is a method of protecting a semiconductor shallowtrench isolation (STI) oxide from etching, the method comprisingproviding means for lowering, if necessary, the upper surface of saidSTI oxide to a level below that of adjacent silicon active areas,providing means for depositing a nitride liner upon said STI oxide andadjacent silicon active areas in a manner effective in defining adepression above said STI oxide, providing means for filling saiddepression with a protective film, providing means for removing saidnitride layer from said adjacent active areas.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 shows a typical starting STI structure.

[0027]FIG. 2 shows the result of an oxide etching process.

[0028]FIG. 3 shows the result of a nitride deposition.

[0029]FIG. 4 shows deposition of a protective planarizing film.

[0030]FIG. 5 shows the result of partially etching the protectiveplanarizing film.

[0031]FIG. 6 shows the result of an etching operation.

[0032]FIG. 7 shows the result of the removal of the planarizing film.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0033] Referring to FIG. 1, there is shown in cross section a typicalstarting structure, namely a silicon wafer 1 comprising, usually, aburied oxide layer (BOX) 2, though this layer could be any suitablesemiconductor material (such as plain silicon, for example), an activearea 3 structure defining one or more shallow trenches filled with aninsulating oxide 4, thereby isolating the active areas 3 on either sideof the trenches from one another.

[0034] Referring to FIG. 2, if the insulating oxide 4 is not alreadybelow the level of the adjacent active areas 3, then it is desirable toetch the STI oxide down to a level below them, as shown in the drawing.The purpose of this is to define a depression over the STI oxide afterdeposition of a nitride liner.

[0035] Any etching method that does not harm the adjacent active areasis sufficient, such as an HF etch or a dry plasma process that isselective to polysilicon. Suitable gases for use in a dry etching plasmaprocess for etching silicon oxides at a more rapid rate than polysiliconinclude CF₄—O₂ and CF₄—H₂ mixtures, wherein the percentage of CF₄ inthese mixtures is generally no greater than 80%, more preferably nogreater than 60%, and most preferably about 50% ±10%. Substantially purefluorocarbon plasmas, such as C₂F₆ may also be utilized.

[0036] Generally, the plasma etching process will be carried out in anetching chamber that may have either or both of plasma enhanced (PE) orreactive ion etch (RIE) capabilities. PE-type etches will generally beconducted at pressures above 100 torr, while RIE etches will generallybe below that pressure. The etches may be performed in batch chambers,such as with barrel etchers, parallel electrode reactors, or hexodeetchers. Larger wafers, generally those not smaller than about 200 mmdiameter may benefit from single-wafer etchers.

[0037] Referring to FIG. 3, a silicon nitride liner 5 is then depositedover the wafer. Optionally, an oxide layer (not shown) may be depositedor grown over the wafer and the nitride layer deposited thereon so as toprotect the silicon surface of the active areas from the stress causedby the nitride layer. The deposition is preferably done in a mannereffective in defining a depression over the STI oxides, hence thetechnique should be conformal to the topography of the lowered STIoxide.

[0038] Typical methods for conformal deposition of the silicon nitrideliner are chemical vapor deposition (CVD) techniques, such as lowpressure (LPCVD), rapid thermal (RTCVD), and plasma enhanced (PECVD)chemical vapor depositions. High density plasma deposition (HDP-CVD)techniques may also be used to perform this operation.

[0039] LPCVD silicon nitride films may generally be formed by reactingdichlorosilane (SiCl₂H₂) with ammonia (NH₃) at temperatures of fromabout 700âC-800âC to form a Si₃N₄ film and HCl and H₂ gasses. LPCVDfilms are desirable for their film uniformity and relatively lowprocessing costs. The rate of LPCVD deposition is correlated to theratio of the concentration (i.e., partial pressure) of dichlorosilanewith respect to that of ammonia. LPCVD depositions are typically carriedout in a hot-wall tube reactor at pressures of from about 0.25 to 2.0torr.

[0040] LPCVD reactions will generally be carried out in a horizontaltube LPCVD batch reactor, also known as a “hot-wall” tube reactor, whichare desirable for their good economy, throughput, uniformity, andability to accommodate even large diameter wafers. Such reactorscomprise a tube, usually quartz, equipped with vacuum producing andheating means, through which the reactive gasses are passed. If theconfiguration is such that the reactive gasses are introduced at one endso as to flow down the length of the tube, then it is generallydesirable to provide temperature ramp means so as to establish atemperature gradient along the length of the tube. This is because thewafers at the source of the gas flow will have the benefit of a higherconcentration of the reactive gasses and will therefore display higherrates of silicon nitride deposition than those wafers downstream. Thiscan be compensated for by increasing the rate of reaction by increasingtemperature downstream. Alternatively, the reactive gasses may beinjected into the chamber through a plurality of openings substantiallyevenly distributed along the length of the reaction chamber. Anothermethod of compensating for the depletion of reactant gasses along thelength of the tube is to increase the rate of gas flow.

[0041] RTCVD silicon nitride films may generally be formed by thereaction of dichlorosilane and ammonia by reacting the gasses in afurnace in which the temperature of the wafer is rapidly ramped totemperatures as high as 1100âC within about five seconds. Temperatureramping rates from 50âC/sec to about 75âC/sec are typically achieved inmost small batch fast ramp (SBFR) furnaces and some of the latest modelsachieve rates as high as 150âC/sec.

[0042] RTCVD methods are desirable for their rapid processing andability to handle large wafers of 300 nm and larger, among otheradvantages. Also, the use of higher temperatures over shorter periods oftime reduces undesirable transient-enhanced diffusion effects.

[0043] Rapid thermal process (RTP) furnaces are commercially availablefrom such companies as Applied Materials and AG Associates, amongothers. Preferred RTP systems will maintain uniform temperature acrossthe width of the wafer during the rapid ramping-up and cooling down oftemperature and will have an accurate means of measuring the wafertemperature so as to control it. A typical Applied Materials RTP willhave a water-cooled reaction chamber, an array of heating lamps, such ashalogen lamps, and a fiber optic temperature probe. The halogen lampswill generally be arrayed above the wafer and have their light directeddownward by collimating light pipes, often with a quartz or fused silicawindow separating the lamps from the reaction chamber. This allows rapidheating and the ability to isolate the chamber so as to evacuate it. Thewafer sits upon an insulative rotating base, the rotation effective insmoothing out any gas flow and light variations. Pyrometers are usuallymounted below the wafer and measure temperature radiating off the backof the wafer at regular intervals, typically 20 times per second,thereby allowing precise computer control over the ramp-up and cool-offof the wafer.

[0044] PECVD silicon nitride films may generally be formed by reactingsilane gas (SiH₄) with either ammonia (NH₃) or nitrogen (N₂) gas in thepresence of electromagnetic radiation in the radio frequency range,thereby depositing a polymer-like Si—N—H material. Reaction temperatureswill typically be from 200âC to 400âC at 0.2 to 0.3 torr andrf-frequencies of from 0.3 to 13.56 MHz. Dual frequency systems,typically combining a high frequency (e.g., about 13.5 MHz) rf-signalwith a low frequency (e.g., 0.3 to 0.6 MHz) rf-signal to control filmstress associated with SiN films. When using ammonia gas, the ratio ofammonia to silane will typically be from about 5 to about 20 partsammonia to silane. When using nitrogen, 100 to 1,000 parts nitrogen tosilane are will typically be used. Generally, PECVD films made withammonia will display better conformalty than those made with nitrogen.

[0045] Three types of PECVD reactors are in wide use, namelyparallel-plate batch reactors, mini-batch radial reactors, and singlewafer reactors.

[0046] Parallel-plate batch reactors have, as the name implies, a set ofparallel plates. The reactor is generally in the form of a verticalcylinder with one plate at the bottom and the other at the top. Thewafers rest on the bottom plate, which can usually be rotated and heatedand the rf-signal is applied to the electrodes.

[0047] A more popular PECVD reactor is the mini-batch radial reactors,which comprises a plurality of deposition stations wherein each a wafersits upon a flat heated electrode. A showerhead-like electrode aboveeach wafer dispenses the reactant gases. These types of reactors arefavored for their high reaction rates and minimal contamination problemsand good uniformity. Uniformity is achieved by moving the wafers fromone station to another for additional depositions, rather thanperforming the entire deposition at once, thereby averaging out anyanomalies at individual stations.

[0048] Single-wafer PECVD reactors, such as those sold by AppliedMaterials, will generally have multiple reactor chambers, each adaptedto contain a single wafer. Each chamber is equipped with a baseelectrode upon which the wafer sits and a showerhead-like gas nozzleelectrode, powered by the rf signal. Heating is usually achieved by aplurality of lamps that provide rapid radiant heating. Film stress maybe controlled by adjusting the rf frequencies or the electrode gap size.

[0049] HDP-CVD silicon nitride films may generally be formed by reactingsilane gas (SiH₄) with either ammonia (NH₃) or nitrogen (N₂) gas in thepresence of electromagnetic radiation and an inert gas, such as Argon(Ar) or Helium (He). Generally, the reaction pressure will be ratherlow, generally below ten mTorr. HDP-CVD techniques are desirable forlaying films down on high-aspect-ratio features.

[0050] HDP-CVD reactors will generally utilize a glow discharge toproduce ions powerful enough to cause sputtering in the material beingdeposited. Glow discharges are a self-sustaining plasma produced byeither or both of a dc-diode type system or an rf-diode system. An inertgas, such as Argon is introduced between a pair of electrodes with astrong enough electric field to ionize the reactant and inert gases to aplasma. Rf-diode systems are preferred because dc-diode systems areunable to sputter insulative materials like silicon nitride and exhibitslower deposition rates in most applications. A preferred rf-diodesystem will be equipped with a magnetron source so as to help confineelectrons near the wafer surface. Commercially popular systems includethose sold under the tradename “Centura” by Applied Materials.

[0051] Referring to FIG. 4, a protective film 6 is deposited. Theprotective planarizing film will preferably be any suitable polymerplastic that is planarizing (i.e., it fills up the depressions ratherthan conforming to the topography of the depressions the way a nitrideCVD deposition does) and for which there exists a selective etch withrespect to silicon nitride (i.e., an etch that will etch the polymer,but not silicon nitride). Commonly available and economical protectivepolymers are those sold for anti-reflective coatings and photo-resistlayers in the lithographic arts, often referred to as “organic spin-on”polymers, which comprise polymer resins-dissolved in solvent. Suchresins will typically have molecular weights in the thousands or tenthousands as measured by gel permeation chromatography, but may even gointo the millions. Novolak binder resins are commonly available anduseful for use in the invention, such as are disclosed in Shiro et al.,U.S. Pat. No. 5,674,657, the teachings of which are incorporated byreference herein in their entirety. A commonly used photoresist is soldunder the designation “HPR-204” by Olin Hunt Specialty Products of NewJersey and comprises mixed meta- and para-cresol novolak binder resinsand a napthaquinone-1,2-diazide-5-sulfonic acid triester of a trihydroxybenzophonene sensitizer dissolved in 85% by weight of ethyl cellusolveacetate, 8.6% by weight butyl acetate, and 5.2% by weight xylene, and1.2% by weight ethyl benzene. Suitable antireflective coatings areco-polymers of benzophenone and bisphenol-A dissolved in an organicsolvent, such as is described in Thomas et al., U.S. Pat. No. 6,207,787,the disclosures of which are incorporated by reference herein in theirentirety. Other suitable antireflective coatings include, but arecertainly not limited to, organic solutions of multifunctional acrylatesand methacrylate monomers, and polyurea and polysulfone polymers.Conformal antireflective coating suitable for use with the invention arealso sold under the tradenames “DUV 30” and “DUV 32” by Brewer Scienc,Inc. of Rolla, Mo. Photoresists and antireflective coatings may also bethinned or diluted by mixing in additional solvent, such as is describedin Daraktchiev, I. S., U.S. Pat. No. 4,996,080, the disclosures of whichare incorporated by reference herein in their entirety. Commerciallyavailable planarizing antireflective coatings suitable for use with theinvention include those sold under the product designations “DUV 30” and“DUV 32”, by Brewer Science, Inc. of Rolla, Mo.

[0052] It is also possible to use a spin-on oxide (e.g., glass spin-on)film for a protective film and then planarize it by chemical mechanicalpolishing (CMP). Alternatively, one may deposit a conformal organic filmand also planarize by CMP. Conformal organic films are generallycomprised of relatively high molecular weight resins, as high as 40,000Daltons and above, dissolved in solvent, such as are described inPavelick et al. U.S. Pat. No. 6,190,839 B1, the disclosures of which areincorporated by reference herein in their entirety. Commerciallyavailable conformal antireflective coatings suitable for use with theinvention include those sold under the product designations “ARC 25”,“DUV 44”, and “DUV 42”, also by Brewer Science, Inc. of Rolla, Mo., andthose sold under the “AR” series trademark by Shipley Company, LLC ofMarlborogh, Mass., particulary those desgnated “AR5” and higher, such as“AR7” and “AR14”.

[0053] Of course, any polymer dissolved in a solvent that issufficiently planarizing, adhering, and possessing the requisiteselectivity will be suited to this invention. Photoresists andantireflective coatings are specifically cited for use with thisinvention because these materials are almost always readily at hand inany semiconductor fabrication facility.

[0054] Referring to FIG. 5, the protective film 6 is recessed such thatonly that portion of the protective film 6 in the depressions over theoxide isolations 4 remain. In the case of an organic polymer protectivefilm, this can be achieved with a plasma etch using oxygen and nitrogengases in the presence of an rf-frequency.

[0055] Referring to FIG. 6, the exposed nitride (i.e., not protected bythe arc) is etched away, preferably with a reactive ion etch (RIE),thereby revealing the active areas 3. Alternatively, a hot phosphoric orsimilar etch may be used, but this procedure is less controllable than adry RIE etch.

[0056] An RIE etch of silicon nitride will generally utilize a CF₄—O₂ orCHF₃—O₂ gas mix, or CH₂F₂ or CH₃F gasses, in the presence of anrf-frequency (e.g., 13.5 MHz) to establish a glow discharge. Typicalreaction pressures are from about 7 to about 6000 mTorr.

[0057] Commercially available RIE systems for use in the inventioninclude those sold under the “Etch Centura” tradename series by AppliedMaterials, among others. Such systems utilize a glow discharge andelectrodes to combine the benefits of sputtering with those of enhancedplasma etching and produce high anisotropic etches.

[0058] Referring to FIG. 7, the protective film 6 may then be etchedaway, leaving a trench oxide 4 covered by a protective nitride cap 5.The active areas may now be precleaned without fear of damage to thetrench oxide 4.

[0059] It is to be understood that all physical quantities disclosedherein, unless explicitly indicated otherwise, are not to be construedas exactly equal to the quantity disclosed, but rather about equal tothe quantity disclosed. Further, the mere absence of a qualifier such as“about” or the like, is not to be construed as an explicit indicationthat any such disclosed physical quantity is an exact quantity,irrespective of whether such qualifiers are used with respect to anyother physical quantities disclosed herein.

[0060] While preferred embodiments have been shown and described,various modifications and substitutions may be made thereto withoutdeparting from the spirit and scope of the invention. Accordingly, it isto be understood that the present invention has been described by way ofillustration only, and such illustrations and embodiments as have beendisclosed herein are not to be construed as limiting to the claims.

What is claimed is:
 1. A method of protecting a semiconductor shallowtrench isolation (STI) oxide from etching, the method comprising:lowering, if necessary, the upper surface of said STI oxide to a levelbelow that of adjacent silicon active areas; depositing a nitride linerupon said STI oxide and adjacent silicon active areas in a mannereffective in defining a depression above said STI oxide; filling saiddepression with a protective film; and removing said nitride layer fromsaid adjacent active areas.
 2. The method of claim 1 wherein saiddeposition of a nitride liner is effected with a chemical vapordeposition.
 3. The method of claim 2 wherein said chemical vapordeposition is one selected from the group: a low pressure chemical vapordeposition; a rapid thermal chemical vapor deposition; a plasma-enhancedchemical vapor deposition; or a high-density plasma chemical vapordeposition.
 4. The method of claim 2 wherein said chemical vapordeposition further comprises reacting a silane derivative with ammonia.5. The method of claim 1 wherein said protective film is an organicpolymer.
 6. The method of claim 5 wherein said organic polymer is aplanarizing polymer.
 7. The method of claim 6 wherein said planarizingprotective polymer is an anti-reflective coating polymer.
 8. The methodof claim 7 wherein said anti-reflective coating polymer is one selectedfrom the group: mixtures of acrylates and methacrylates; mixtures ofpolyurea and polysulfone polymers; and copolymers of benzophenone andbisphenol-A.
 9. The method of claim 6 wherein said planarizingprotective polymer is a photo-resist polymer.
 10. The method of claim 9wherein said photo-resist polymer comprises a novolak resin.
 11. Themethod of claim 1 wherein said protective film is a spin-on oxide. 12.The method of claim 1, wherein said protective film is conformal and isplanarized by chemical mechanical polishing.
 13. The method of claim 1wherein said filling of said depression with protective film comprises:depositing a layer of said protective film over said nitride layer; andrecessing said protective film such that said protective film remainsonly in said depression.
 14. The method of clam 13 wherein saidprotective film is an organic polymer and said recessing is effectedwith a plasma etch.
 15. The method of claim 1 further comprisingremoving said protective film from said depression.
 16. The method ofclaim 15 wherein said removing of said protective film is accomplishedwith a reactive ion etch.
 17. A method of protecting a semiconductorshallow trench isolation (STI) oxide from etching, the methodcomprising: lowering, if necessary, the upper surface of said STI oxideto a level below that of adjacent silicon active areas; optionallydepositing a silicon oxide layer over said STI oxide and adjacentsilicon active areas effective in protecting said adjacent siliconactive layers from stresses induced by a conformal nitride linerdeposited thereon; executing a chemical vapor deposition to deposit saidconformal nitride liner upon said STI oxide and adjacent silicon activeareas in a manner effective in defining a depression above said STIoxide; covering said nitride liner with a protective film comprising anorganic polymer; recessing said protective film with a plasma etch, suchthat said protective film remains only in said depression; removing saidnitride layer from said adjacent active areas with a reactive ion etch;and removing said protective film from said depression with a plasmaetch.
 18. A semiconductor structure, comprising a plurality of activeareas separated by one or more shallow trench isolations wherein onlysaid shallow trench isolations are covered by a protective layer ofsilicon nitride.
 19. A semiconductor structure comprising: a pluralityof active areas separated by one or more shallow trench isolations; saidactive areas and shallow trench isolations covered by a layer of siliconnitride, wherein said layer of silicon nitride comprises depressionsover said shallow trench isolations; a protective film disposed in saiddepressions.
 20. A method of protecting a semiconductor shallow trenchisolation (STI) oxide from etching, the method comprising: providingmeans for lowering, if necessary, the upper surface of said STI oxide toa level below that of adjacent silicon active areas; providing means fordepositing a nitride liner upon said STI oxide and adjacent siliconactive areas in a manner effective in defining a depression above saidSTI oxide; providing means for protecting said adjacent silicon activeareas from stresses induced by said nitride liner; providing means forfilling said depression with a protective film; providing means forremoving said nitride layer from said adjacent active areas.